The present invention relates to wideband circuits, and in particular, to wideband circuits that may be used between circuit stages.
Electronic circuits are typically built in stages. For example, an analog circuit may include one or more amplifiers connected in series, wherein each amplifier constitutes a stage of the circuit with a particular amplification strength (i.e., gain). Other stages may include filters, mixers, analog-to-digital converters (“ADC”), digital-to-analog converters (“DAC”), a variety of different amplifiers such as power amplifiers or low noise amplifiers, or other circuit stages. Digital circuits may also be connected in stages as is well known by those skilled in the art.
FIG. 1A illustrates one problem associates with circuit stages. A first circuit stage 101 receives an input signal “In” and provides an output signal to the input of a second circuit stage 102, which in turn generates an output signal “Out.” In many stages, the output of the stage includes some kind of output impedance for translating currents at the output into voltages. The output impedance in this example is represented by a resistor (“RL”) 103 connected between the output and a power supply Vdd. The output node of any circuit stage will have a corresponding parasitic output capacitance. Parasitic output capacitance may be due to a variety of well-known factors such as the capacitance introduced by conductive traces (i.e., routing capacitance), the gate-to-drain capacitance or drain-to-substrate capacitance of MOS transistors, or the capacitance of contacts between a conductive trace and a resistor terminal to name just a few. All the parasitic capacitances of the output node of stage 101 are represented by capacitor Cp1. Similarly, the input nodes of circuit stages will also have associated parasitic capacitances stemming from, for example, the gate capacitance of MOS transistors and a variety of other well-known sources. All the parasitic capacitances of the input node of stage 102 are represented by capacitor Cp2.
FIG. 1B shows an equivalent circuit of FIG. 1A and the corresponding frequency response. One problem associated with parasitic capacitance is that it can effectively narrow the bandwidth of signal frequencies that can be coupled between stages of an electronic circuit. For example, signals at the output of stage 101 will see a low pass filter caused by the parallel combination of the output impedance and the parasitic capacitances. In FIG. 1B, the combined parasitic capacitances are represented by CT. The plot in FIG. 1B shows the bandwidth of the circuit where the value of CT and RL are as follows:CT=600 fFRL=50Ω.The output signal of stage 101 will be attenuated by 3 dB at the following frequency:f3db=1/2πR(Cp1+Cp2).For comparison with plots below, FIG. 1B shows the 1 dB frequency rather than the 3 dB frequency. However, in this example the 1 dB frequency is about one-half of the 3 dB frequency. Therefore, to increasing the bandwidth of the circuit, either the resistance or capacitance must be reduced. Since resistance is typically used to set the gain of the previous stage, it is generally desirable to reduce the parasitic capacitance. However, in any given process technology or application, there are practical limits to how far parasitic capacitances can be reduced. Thus, it is generally desirable to reduce the “effects” of parasitic capacitance on the signals that are being processed by each stage of the circuit.
FIG. 1C is a prior art interstage circuit 100C. In this circuit, a first stage includes transistor (M1) 101 having a gate coupled to receive an input signal and a drain having a parasitic capacitance CpM1. The output node of transistor 101 has a further parasitic capacitance CpR from the parasitic capacitance due to routing. Since the capacitances are in parallel, these parasitic capacitances will add and can be represented by a single capacitor as shown. Similarly, a second stage includes transistor (M2) 102 having a gate coupled to receive the output signal of the previous stage. The input to the second stage has a parasitic capacitance of CpM2. A passive network 104 is provided between the output of transistor 101 and the input of transistor 102. In this circuit, the input of the passive network is coupled to the drain output of transistor 101 and the output of the passive network 104 is coupled to the gate of transistor 102. Network 104 includes an inductor (L2) 105, input capacitances CpM1 and CpR, output capacitance CpM2, and resistor 103. Network 104 is a third-order filter between the output of the first stage and the input of the second stage. In this circuit, parasitic capacitances are absorbed into network 104 and the overall bandwidth of the system may be increased. In such a case, the output of the network includes the load for setting the gain of the previous stage. However, the bandwidth is typically limited by the parasitic capacitance at the input of the second stage (here, the gate capacitance of M2). Thus, for a given gain requirement, the bandwidth will typically be constrained by the capacitive loading at the output of the filter caused by the parasitic input capacitance of M2.
FIG. 1D illustrates a similar approach using a higher order network. Network 120 is a 5th-order filter having an input connected to the output of the first stage (i.e., the drain of M1) and an output connected to the input of the second stage (i.e., the gate of M2). Network 120 includes inductors (L2) 121 and (L3) 123, input capacitances CpM1 and CpR, intermediate capacitance (Cf1) 122, output capacitance CpM2, and resistor 103. As before, the resistor at the network output may be used to set the load impedance (i.e., gain), and the parasitic capacitances are absorbed into the input and output of network 120. Thus, the bandwidth of the system is increased.
While the prior art circuits in FIGS. 1C and 1D are useful in increasing the bandwidth, such circuits are still limited by the size of the parasitic capacitances. For example, the input of a stage implemented using MOS devices will typically have a large parasitic gate capacitance. In many applications it may be desirable to optimize the gain and bandwidth of the circuit. Accordingly, for a given gain requirement, smaller parasitic capacitance values would be required. Similarly, it is often desirable to increase the size of the M2 device so that the subsequent stage can deliver more current, for example. Thus, it is generally desirable to maximize the parasitic capacitance that can be tolerated at the input of the second stage while maintaining maximum bandwidth and gain. Thus, there is a need for improved wideband circuits and methods.